1. Field of the Invention
The present invention relates to a flash memory. More particularly, the present invention relates to a flash memory that has a smaller distance of separation between memory cells.
2. Description of the Related Art
FIG. 1 is a top view of a conventional flash memory, and FIG. 2 is a schematic cross-sectional view along line II-II′ of FIG. 1. As shown in FIGS. 1 and 2, diffusion regions 102 and isolation regions 104 are alternately laid down in the y direction on a substrate 100. Furthermore, a plurality of control gates 106 are aligned in the x direction on the substrate 100. The floating gate (not shown) and the tunneling dielectric layer (not shown) of each memory cell are formed in an overlapping area 110 of each diffusion region 102 and the control gate 106. The diffusion region 102 on one side of the control gate 106 serves as a source region 108a while the diffusion region 102 on the other side serves as a drain region 108b. In general, the drain regions 108b in the same row are electrically connected to a conductive line (not shown) through a plurality of contacts 112. In contrast, the source regions 108a in the same row as shown in FIG. 2 are electrically connected to a line (not shown) through a source pick-up line 116 and contacts 118 set up between the two isolation regions 104, for example, by removing the isolation structures (that is, the isolation regions 104) within the source regions 108a and forming a doped region 114 that connects all the source regions 108a in the same row inside the exposed substrate.
However, a considerable number of contacts are formed in the aforementioned structure, making it quite difficult to reduce the area occupied by a flash memory. In other words, the aforementioned structure is quite out of line with the trend toward miniaturizing semiconductor devices.